1. Field of the Invention
The present invention relates to a technology for enabling high-speed transmission of signals between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or a plurality of cabinets and, more particularly, to a data receiving circuit and a clock recovery circuit that uses a feedback-loop-type clock signal generating circuit.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, and the like have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between a storage device such as a SRAM or DRAM (memory) and a processor (i.e., between LSIs), for example, has been widening year by year, and in recent years, this speed gap has been becoming a bottleneck impeding performance improvement for a computer as a whole. Furthermore, with increasing integration and increasing size of semiconductor chips, the speed of signal transmission between elements or circuit blocks within a chip is becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset is also becoming a factor limiting the overall performance of the system.
Generally, in high-speed signal transmission between circuit blocks or chips or between cabinets, a clock used to discriminate between data “0” and data “1”, is generated (recovered) at the receiving circuit. The recovered clock is adjusted by a feedback circuit in the receiving circuit so that the clock is maintained within a certain phase range with respect to the received signal in order to ensure correct signal reception at all times. The process of recovering the clock and discriminating the data using the thus recovered clock is called the CDR (Clock and Data Recovery). The CDR is the most important function for high-speed data reception, and various schemes are being studied. There is thus a strong need to provide a data receiving circuit (clock recovery circuit) capable of handling high-speed and accurate signal transmission using CDR.
To address the recent increase in the amount of data transmission between LSIs or between boards or cabinets, signal transmission speed per pin must be increased. This is also necessary to avoid an increase in package cost, etc. due to an increased pin count. As a result, inter-LSI signal transmission speeds exceeding 2.5 Gbps have been achieved in recent years, and it is now desired to achieve extremely high speeds (high-speed signal transmission) reaching or even exceeding 10 Gbps.
To speed up the signal transmission between LSIs, for example, it is required that the receiving circuit operates with adequately accurate timing for each incoming signal (for data detection and discrimination). It is known in the prior art to provide in a signal receiver circuit a clock recovery circuit (CDR) that uses a feedback loop type clock signal generating circuit in order to generate a clock (internal clock) with such accurate timing.
Before proceeding to the detailed description of the preferred embodiments of the data receiving circuit (clock recovery circuit) according to the present invention, data receiving circuits according to the prior art and the related art and their associated problems will be described with reference to drawings.
FIG. 1 is a block diagram showing one example of the prior art data receiving circuit, wherein the circuit is configured as a 4-way.times.2 type interleaving circuit using CDR. FIG. 2 is a diagram showing the timing of each signal in the data receiving circuit of FIG. 1.
In FIG. 1, reference numerals 110 to 113 are data discrimination units (flip-flops for data discrimination), 120 to 123 are boundary detection units (flip-flops for boundary detection), and 131 and 132 are data and boundary conversion circuits, respectively. Further, reference numeral 141 is a data discrimination clock generating circuit, 142 is a boundary detection clock generating circuit, 105 is a phase-difference/digital-code conversion circuit (PDC: Phase to Digital Converter), and 106 is a digital filter. On the other hand, reference character DIL is a data input line, DCL is a data discrimination clock line, BCL is a boundary detection clock line, and DFL and BFL are data and boundary feedback lines, respectively.
As shown in FIG. 1, in the prior art data receiving circuit, the data input line DIL which carries, for example, 10-Gbps data is connected to the inputs of the four data discrimination units 110 to 113 and four boundary detection units 120 to 123, which respectively latch the data by their corresponding 2.5-Hz clocks.
More specifically, as shown in FIGS. 1 and 2, the data discrimination units 110 to 113 are supplied with four phase clocks CLKd0 to CLKd3, respectively, from the data discrimination clock generating circuit 141. the clocks being 2.5 GHz in frequency and differing in phase by 90.degree. (for example, the phases are 45.degree., 135.degree., 225.degree., and 315.degree., respectively). The input data are latched with the phase timings of 45.degree., 135.degree., 225.degree., and 315.degree., respectively, and the received data DT0 to DT3 are supplied to the conversion circuit 131. The conversion circuit 131 converts the received data DT0 to DT3, each being one-bit data synchronized to the 2.5-Hz clock, into 32-bit data (DT [31:0]) synchronized to a 312.5 MHz clock, and supplies this received data (DT [31:0]) to the circuit (an internal circuit) at the next stage, as well as to the phase-difference/digital-code conversion circuit 105.
On the other hand, the boundary detection units 120 to 123 are supplied with four phase clocks CLKb0 to CLKb3, respectively, from the boundary detection clock generating circuit 142, the clocks being 2.5 GHz in frequency and differing in phase by 90.degree. (for example, the phases are 0.degree., 90.degree., 180.degree., and 270.degree., respectively). Boundaries of the input data are detected with the chase timings of 0.degree., 90.degree., 180.degree., and 270.degree., respectively, and the boundary detection data BT0 to BT3 are supplied to the conversion circuit 132. The conversion circuit 132 converts the boundary detection data BT0 to BT3, each being one-bit data synchronized to the 2.5-GHz clock, into 32-bit data (BT [31:0]) synchronized to a 312.5 MHz clock, and supplies the thus converted data to the phase-difference/digital-code conversion circuit 105. Here, the four phase clocks CLKd0 to CLKd3 output from the data discrimination clock generating circuit 141 have a chase difference of 45.degree. with respect to the four phase clocks CLKb0 to CLKb3 output from the boundary detection clock generating circuit 142.
The phase-difference/digital-code conversion circuit 105 compares the thus input received-data DT [31:0] and boundary detection data BT[31:0], and outputs 7-bit phase difference information (PDCODE [6:0, −32 to +32] to the digital filter 106. The digital filter 106 feeds back a 6-bit resolution data discrimination phase control code to the data discrimination clock generating circuit 141 via the feedback line DFL, and also feeds back a 6-bit resolution boundary detection phase control code to the boundary detection clock generating circuit 142 via the feedback line BFL. In FIG. 2, the data latch timings (rise timings) of the boundary detection clocks CLKb0 to CLKb3 are at the boundary positions of the input data; here, the diagram is developed by assuming that the boundary detection data BT0 to BT3 latched by the boundary detection units 120 to 123 are 1, 1, 0, 1, and so on.
FIG. 3 is a block diagram showing the data discrimination clock generating circuit 141 (boundary detection clock generating circuit 142) in the data receiving circuit of FIG. 1.
As shown in FIG. 3, the data discrimination clock generating circuit 141 comprises a mixer circuit 1411 and a digital-to-analog converter (DAC) 1413. The mixer circuit 1411 receives a clock signal (four-phase clock) and an output of the DAC 1413 and, from the four-phase clock, generates a pair of signals differing in phase by 90 degrees and creates a chase intermediate between them. It then generates a clock by adding a phase shift defined by a weight (the output of the DAC 1413) to the signal having the intermediate phase, thus generating the data detection clock CLKd (CLKd0, CLKd1, CLKd2, CLKd3). In like manner, the boundary detection clock generating circuit 142 generates the boundary detection clock CLKb (CLKb0, CLKb1, CLKb2, CLKb3).
The mixer circuit 1411 controls the phase based on an electric current value representing the weight; here, the weight for the phase adjustment is created in the phase-difference/digital-code conversion circuit 105 by digitally comparing the chases of the external input data (or input clock) and internal clock (the data discrimination clock CLKd and boundary detection clock CLKb) based on the outputs of the data discrimination units 110 to 113 and boundary detection units 120 to 123, and is supplied as the phase control code (data discrimination phase control code) to the DAC 1413 through the digital filter 106.
The DAC 1413 receives a constant current as well as the chase control code, converts the phase adjusting weight into an electric current, and supplies the electric current to the mixer circuit 1411. The phase of the clock CLKd (CLKb) is adjusted based on the amount of change of the electric current.
Here, the term “clock recovery circuit (CDR)” is used to focus attention on the fact that the data discrimination clock is recovered from the input signal, while the term “data receiving circuit”-0 is used to focus attention on the fact that the data discrimination circuit, using the recovered clock, discriminates the data carried in the input signal, and outputs the data as the received data.
In the data receiving circuit (clock recovery circuit) shown in FIGS. 1 and 2, if the boundary detection units 120 to 123 used for phase comparison (clock recovery) are constructed from the same circuits as those used to construct the data discrimination units 110 to 113, systematic phase shifting does not occur, so that not only can the clock recovery be achieved with high accuracy, but the sensitivity of the phase comparison can also be enhanced.
FIG. 4 is a diagram showing an example of latch timing for input signal data and boundaries.
In FIG. 4, reference characters DATA [i−2], DATA [i−1], DATA [i], and DATA [i+1], for example, indicate the ideal timings for latching (discriminating) the data by the data discrimination units 110, 111, 112, and 113. while BDATA [i−2], BDATA [i−1], BDATA [i], and BDATA [i+1], for example, indicate the ideal timings for latching (detecting) the boundaries by the boundary detection units 120, 121, 122, and 123.
The prior art and the related art and their associated problems will be described in detail later with reference to the accompanying drawings.